1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more particularly, to a semiconductor device including a vertical transistor and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2008-310724, filed Dec. 5, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, with progress in microfabrication techniques, miniaturization and increases in the capacity of semiconductor devices have rapidly progressed. As a small-sized large-capacity semiconductor device, for example, there is a vertical transistor.
The vertical transistor is obtained by forming a cylindrical semiconductor (hereinafter, referred to as a silicon pillar) on a semiconductor substrate, providing an upper diffusion region on a front end of the silicon pillar, providing a lower diffusion region on a base end side, providing a gate electrode on a sidewall thereof with a gate insulating film interposed therebetween, and placing a semiconductor element such as a transistor or a memory cell along a height direction of the silicon pillar.
In the vertical transistor, since the height direction of the silicon pillar may be a gate length direction of the semiconductor element, it is possible to ensure a gate length equal to or more than a predetermined length and prevent a short channel effect.
In the vertical transistor, since a plurality of semiconductor elements can be placed so as to be superposed in the height direction of the silicon pillar, it is possible to realize high density without increasing the area of the semiconductor substrate.
In addition, the vertical transistor has excellent characteristics in which a semiconductor element of a partial depletion-type or complete depletion type structure is relatively easily formed and a device with a high speed or a semiconductor element with low power consumption can be formed using an electric field concentration effect.
For the above reasons, the vertical transistor is expected as a semiconductor device capable of realizing, at low cost, a small size and a large capacity.
Japanese Unexamined Patent Application, First Publication, No. 2003-017585 discloses a semiconductor memory device and a method of manufacturing the same, and discloses a vertical cell transistor. In addition, it discloses that the vertical cell transistor can suppress a short channel effect and can improve a retention property.
However, since the vertical cell transistor has a configuration in which a word line is formed just on a gate electrode, a distance between the word line and a contact provided on an upper diffusion layer shortens and a short circuit is formed between the gate electrode and the upper diffusion layer.
Japanese Unexamined Patent Application, First Publication, No. 2004-221242 discloses a semiconductor integrated circuit device and a method of manufacturing the same and discloses means for improving embedding characteristics between vertical MISFETs.
Japanese Unexamined Patent Application, First Publication, No. 2004-247656 discloses a semiconductor device and a method of manufacturing the same and discloses a configuration and means for avoiding an electrical short circuit of a contact plug connected to a gate electrode and a source/drain region by controlling the sizes and the positions of a device separation region and a polysilicon film.
Japanese Unexamined Patent Application, First Publication, No. 2008-072051 discloses a non-volatile semiconductor memory device and a method of manufacturing the same and discloses a configuration and means for preventing a short circuit even when variations of processing size or misalignment at lamination are generated, by controlling the diameter of a connection portion of a contact plug. However, even when these techniques are used, it is difficult to solve the above problems.